2209 search results - page 323 / 442 » A high performance JPEG2000 architecture |
DAC
2004
ACM
14 years 10 months ago
2004
ACM
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
DAC
2004
ACM
14 years 10 months ago
2004
ACM
Bounded Model Checking (BMC) relies on solving a sequence of highly correlated Boolean satisfiability (SAT) problems, each of which corresponds to the existence of counter-example...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
WWW
2001
ACM
14 years 9 months ago
2001
ACM
The wealth of information on the web makes it an attractive resource for seeking quick answers to simple, factual questions such as "who was the first American in space?"...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...