Sciweavers

2209 search results - page 334 / 442
» A high performance JPEG2000 architecture
Sort
View
IPPS
1997
IEEE
14 years 1 months ago
DPF: A Data Parallel Fortran Benchmark Suite
We present the Data Parallel Fortran (DPF) benchmark suite, a set of data parallel Fortran codes forevaluatingdata parallel compilers appropriatefor any target parallel architectu...
Y. Charlie Hu, S. Lennart Johnsson, Dimitris Kehag...
ANCS
2007
ACM
14 years 1 months ago
Experimenting with buffer sizes in routers
Recent theoretical results in buffer sizing research suggest that core Internet routers can achieve high link utilization, if they are capable of storing only a handful of packets...
Neda Beheshti, Jad Naous, Yashar Ganjali, Nick McK...
DATE
2004
IEEE
122views Hardware» more  DATE 2004»
14 years 25 days ago
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...
Markus Lorenz, Peter Marwedel
DSRT
2004
IEEE
14 years 25 days ago
HLA-Based Distributed Simulation Cloning
Distributed simulation cloning technology is designed to analyze alternative scenarios of a distributed simulation concurrently within the same execution session. The goal is to o...
Dan Chen, Stephen John Turner, Boon-Ping Gan, Went...
ISLPED
1995
ACM
112views Hardware» more  ISLPED 1995»
14 years 20 days ago
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors
Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog ...
Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. ...