2209 search results - page 57 / 442 » A high performance JPEG2000 architecture |
FPGA
1997
ACM
14 years 1 months ago
1997
ACM
ct High-capacity FPGAs pose device architects with a variety of problems. The most obvious of these problems is interconnect capacity. Others include interconnect performance, cloc...
ANCS
2009
ACM
13 years 6 months ago
2009
ACM
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
ECIS
2001
13 years 10 months ago
2001
This paper describes the construction of a generic data model for strategic planning in Public Administration (PA). This model is presented at two distinct levels corresponding to...
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
HOTI
2005
IEEE
14 years 2 months ago
2005
IEEE
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...