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DATE
2009
IEEE
85views Hardware» more  DATE 2009»
14 years 2 months ago
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems
- Parallel architectures have become an increasingly popular method in which to achieve high performance with low power consumption. In order to leverage these benefits, applicatio...
Abelardo Jara-Berrocal, Ann Gordon-Ross
ERSA
2008
103views Hardware» more  ERSA 2008»
13 years 9 months ago
A Hardware Accelerator for k-th Nearest Neighbor Thinning
This paper presents an accelerator for k-th nearest neighbor thinning, a run time intensive algorithmic kernel used in recent multi-objective optimizers. We discuss the thinning al...
Tobias Schumacher, Robert Meiche, Paul Kaufmann, E...
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
14 years 1 months ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
12 years 11 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
ACIVS
2005
Springer
14 years 1 months ago
Reduced-Bit, Full Search Block-Matching Algorithms and Their Hardware Realizations
Abstract. The Full Search Block-Matching Motion Estimation (FSBME) algorithm is often employed in video coding for its regular dataflow and straightforward architectures. By iterat...
Vincent M. Dwyer, Shahrukh Agha, Vassilios A. Chou...