172 search results - page 24 / 35 » A high performance reconfigurable Motion Estimation hardware... |
CODES
2009
IEEE
14 years 6 days ago
2009
IEEE
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
ICIP
2006
IEEE
14 years 9 months ago
2006
IEEE
This paper proposes a hardware architecture of a video noise estimation algorithm capable of real-time processing. The objectives consist of adapting a computationally demanding n...
ARC
2009
Springer
14 years 4 days ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
EUROPAR
2009
Springer
14 years 3 days ago
2009
Springer
Multicore architectures featuring specialized accelerators are getting an increasing amount of attention, and this success will probably influence the design of future High Perfor...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...