159 search results - page 12 / 32 » A high throughput 3D-bus interconnect for network processors |
STOC
1991
ACM
13 years 11 months ago
1991
ACM
d Abstract) James Aspnes Maurice Herlihyy Nir Shavitz Digital Equipment Corporation Cambridge Research Lab CRL 90/11 September 18, 1991 Many fundamental multi-processor coordinati...
CODES
2003
IEEE
14 years 19 days ago
2003
IEEE
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Workstation clusters equipped with high performance interconnect having programmable network processors facilitate interesting opportunities to enhance the performance of parallel...
CISIS
2009
IEEE
2009
IEEE
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
14 years 2 months ago
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...