159 search results - page 16 / 32 » A high throughput 3D-bus interconnect for network processors |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
VLSISP
2008
13 years 7 months ago
2008
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip da...
ANCS
2006
ACM
13 years 11 months ago
2006
ACM
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
PC
1998
13 years 7 months ago
1998
This paper investigates communication strategies for interconnecting heterogeneous parallel systems. As the speed of processors and parallel systems keep on increasing over the ye...