159 search results - page 20 / 32 » A high throughput 3D-bus interconnect for network processors |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, inte...
HPDC
2009
IEEE
14 years 2 months ago
2009
IEEE
Since the advent of electronic computing, the processors’ clock speed has risen tremendously. Now that energy efficiency requirements have stopped that trend, the number of proc...
AINA
2007
IEEE
14 years 1 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
ANCS
2005
ACM
14 years 28 days ago
2005
ACM
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...
APCSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...