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» A high throughput 3D-bus interconnect for network processors
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TC
2008
13 years 7 months ago
An Efficient and Deadlock-Free Network Reconfiguration Protocol
Component failures and planned component replacements cause changes in the topology and routing paths supplied by the interconnection network of a parallel processor system over ti...
Olav Lysne, José Miguel Montañana, J...
PODC
2011
ACM
12 years 10 months ago
Robust network supercomputing without centralized control
Internet supercomputing is becoming an increasingly popular means for harnessing the power of a vast number of interconnected computers. This comes at a cost substantially lower t...
Seda Davtyan, Kishori M. Konwar, Alexander A. Shva...
MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
14 years 2 months ago
SCARAB: a single cycle adaptive routing and bufferless network
As technology scaling drives the number of processor cores upward, current on-chip routers consume substantial portions of chip area and power budgets. Since existing research has...
Mitchell Hayenga, Natalie D. Enright Jerger, Mikko...
PPL
2008
185views more  PPL 2008»
13 years 7 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
CCGRID
2001
IEEE
13 years 11 months ago
Latency Hiding in Dynamic Partitioning and Load Balancing of Grid Computing Applications
The Information Power Grid (IPG) concept developed by NASA is aimed to provide a metacomputing platform for large-scale distributed computations, by hiding the intricacies of a hig...
Sajal K. Das, Daniel J. Harvey, Rupak Biswas