159 search results - page 4 / 32 » A high throughput 3D-bus interconnect for network processors |
HIPEAC
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
JSS
2006
13 years 7 months ago
2006
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
ICES
2010
Springer
13 years 5 months ago
2010
Springer
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
ICC
1997
IEEE
13 years 11 months ago
1997
IEEE
Multicast capability can be incorporated into any interconnection networks by using a general packet replication scheme previously proposed in [4]. The network can then be used fo...