159 search results - page 5 / 32 » A high throughput 3D-bus interconnect for network processors |
TCAD
2010
13 years 2 months ago
2010
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
NOCS
2010
IEEE
13 years 5 months ago
2010
IEEE
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
High-radix switches are desirable building blocks for large computer interconnection networks, because they are more suitable to convert chip I/O bandwidth into low latency and lo...
CLUSTER
2006
IEEE
14 years 1 months ago
2006
IEEE
Interconnect speeds currently surpass the abilities of today’s processors to satisfy their demands. The throughput rate provided by the network simply generates too much protoco...
SLIP
2003
ACM
14 years 17 days ago
2003
ACM
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...