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» A holistic methodology for network processor design
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IJES
2008
128views more  IJES 2008»
13 years 7 months ago
On-chip implementation of multiprocessor networks and switch fabrics
: On-chipimplementationofmultiprocessorsystemsneedstoplanarisetheinterconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor ...
Terry Tao Ye, Giovanni De Micheli
IPPS
2005
IEEE
14 years 1 months ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
CF
2007
ACM
13 years 11 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
VLSID
2004
IEEE
170views VLSI» more  VLSID 2004»
14 years 8 months ago
On-chip networks: A scalable, communication-centric embedded system design paradigm
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf
MSWIM
2004
ACM
14 years 1 months ago
Detailed models for sensor network simulations and their impact on network performance
Recent trends in sensor network simulation can be divided between less flexible but accurate emulation based approach and more generic but less detailed network simulator models....
Maneesh Varshney, Rajive Bagrodia