89 search results - page 17 / 18 » A logic for ignorance |
VLSISP
2008
13 years 7 months ago
2008
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
ISSTA
2009
ACM
14 years 1 months ago
2009
ACM
Exception analysis and points-to analysis are typically done in complete separation. Past algorithms for precise exception analysis (e.g., pairing throw clauses with catch stateme...
INFOCOM
2000
IEEE
13 years 11 months ago
2000
IEEE
Abstract— Knowledge of the up-to-date physical topology of an IP network is crucial to a number of critical network management tasks, including reactive and proactive resource ma...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
In this paper, we revisit the classical problem of functional decomposition [1, 2] that arises so often in logic synthesis. One basic problem that has remained largely unaddressed...