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» A low complexity hardware architecture for motion estimation
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ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 28 days ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 4 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
ICIP
2006
IEEE
14 years 9 months ago
Backward Channel Aware Wyner-Ziv Video Coding
Wyner-Ziv video coding is a coding method that exploits source statistics at the decoder. Many Wyner-Ziv video coding schemes encode a video sequence into two types of frames, key...
Limin Liu, Zhen Li, Edward J. Delp
EGH
2004
Springer
14 years 1 months ago
A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications
The real time 3D graphics becomes one of the attractive applications for 3G wireless terminals although their battery lifetime and memory bandwidth limit the system resources for ...
Ju-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo
ICRA
2003
IEEE
104views Robotics» more  ICRA 2003»
14 years 28 days ago
Enhancing the reactive capabilities of integrated planning and control with cooperative extended kohonen maps
— Despite the many significant advances made in robot motion research, few works have focused on the tight integration of high-level deliberative planning with reactive control ...
Kian Hsiang Low, Wee Kheng Leow, Marcelo H. Ang Jr...