315 search results - page 44 / 63 » A low complexity hardware architecture for motion estimation |
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigu...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— We extend a 3D differential-operator-based filter architecture to a 3D IIR FPGA filter circuit implementation employing a recently proposed scanned-array method, which uses a s...
DATE
2010
IEEE
13 years 12 months ago
2010
IEEE
We have proposed (, )-based flow regulation to reduce delay and backlog bounds in SoC architectures, where bounds the traffic burstiness and the traffic rate. The regulation is co...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
Cryptanalysis of symmetric and asymmetric ciphers is a challenging task due to the enormous amount of involved computations. To tackle this computational complexity, usually the e...
EUROPAR
2009
Springer
14 years 8 days ago
2009
Springer
Multicore architectures featuring specialized accelerators are getting an increasing amount of attention, and this success will probably influence the design of future High Perfor...