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ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Design methodology for IRA codes
Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of Low-...
Frank Kienle, Norbert Wehn
DAC
2009
ACM
14 years 8 months ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...
WSC
1997
13 years 9 months ago
The Power and Performance of Proof Animation
Proof Animation™ 4.0 is a family of products for animating discrete event simulations. Proof is available in a variety of versions, including an inexpensive, student version, mi...
James O. Henriksen
ASYNC
1998
IEEE
122views Hardware» more  ASYNC 1998»
13 years 12 months ago
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...
Martin Benes, Steven M. Nowick, Andrew Wolfe
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 11 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...