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» A low power FPGA routing architecture
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DAC
2007
ACM
14 years 8 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
DATE
2009
IEEE
132views Hardware» more  DATE 2009»
14 years 2 months ago
An efficent dynamic multicast routing protocol for distributing traffic in NOCs
Nowadays, in MPSoCs and NoCs, multicast protocol is significantly used for many parallel applications such as cache coherency in distributed shared-memory architectures, clock sync...
Masoumeh Ebrahimi, Masoud Daneshtalab, Mohammad Ho...
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
14 years 23 days ago
Register binding and port assignment for multiplexer optimization
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
Deming Chen, Jason Cong
ICES
2005
Springer
177views Hardware» more  ICES 2005»
14 years 26 days ago
Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs
Evolvable Hardware arises as a promising solution for automatic digital synthesis of digital and analog circuits. During the last decade, a special interest has been focused on evo...
Andres Upegui, Eduardo Sanchez
APNOMS
2007
Springer
14 years 1 months ago
A Routing Scheme for Supporting Network Mobility of Sensor Network Based on 6LoWPAN
Network Mobility (NEMO) and IPv6 over Low power Wireless PAN (6LoWPAN) protocols are the two significant important technologies in the current networking research areas and seem to...
Jin Ho Kim, Choong Seon Hong, Koji Okamura