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» A low power FPGA routing architecture
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IPPS
2006
IEEE
14 years 1 months ago
Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
Among different wireless LAN technologies 802.11a has recently become popular due to its high throughput, large system capacity, and relatively long range. In this paper, we prop...
Maryam Mizani, Daler N. Rakhmatov
INFOCOM
2005
IEEE
14 years 28 days ago
IPStash: a set-associative memory approach for efficient IP-lookup
—IP-Lookup is a challenging problem because of the increasing routing table sizes, increased traffic, and higher speed links. These characteristics lead to the prevalence of hard...
Stefanos Kaxiras, Georgios Keramidas
DATE
2007
IEEE
107views Hardware» more  DATE 2007»
14 years 1 months ago
Routing table minimization for irregular mesh NoCs
The majority of current Network on Chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unreali...
Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam...
GI
2004
Springer
14 years 22 days ago
A Low-Cost Solution for Frequent Symmetric Key Exchange in Ad-hoc Networks
: Next to authentication, secure key exchange is considered the most critical and complex issue regarding ad-hoc network security. We present a low-cost, (i.e. low hardware-complex...
Markus Volkmer, Sebastian Wallner
DAC
2006
ACM
14 years 8 months ago
An automated, reconfigurable, low-power RFID tag
This paper describes an ultra low power active RFID tag and its automated design flow. RFID primitives to be supported by the tag are enumerated with RFID macros and the behavior ...
Alex K. Jones, Raymond R. Hoare, Swapna R. Donthar...