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» A low power high performance switched-current multiplier
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HOTI
2005
IEEE
14 years 1 months ago
High-Speed and Low-Power Network Search Engine Using Adaptive Block-Selection Scheme
A partitioned TCAM-based search engine is presented that increases packet forwarding rate multiple times over traditional TCAMs. The model works for IPv4 and IPv6 packet forwardin...
Mohammad J. Akhbarizadeh, Mehrdad Nourani, Rina Pa...
ANCS
2008
ACM
13 years 9 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
DAC
1998
ACM
14 years 8 months ago
Reducing Power in High-Performance Microprocessors
Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is ...
Vivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav M...
VLSID
2006
IEEE
240views VLSI» more  VLSID 2006»
14 years 7 months ago
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition
Logarithmic Number Systems (LNS) offer a viable alternative in terms of area, delay and power to binary number systems for multiplication and division operations in signal process...
Venkataraman Mahalingam, N. Ranganathan
ISVLSI
2008
IEEE
143views VLSI» more  ISVLSI 2008»
14 years 1 months ago
BTB Access Filtering: A Low Energy and High Performance Design
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras