45 search results - page 8 / 9 » A low-area interconnect architecture for chip multiprocessor... |
MOBICOM
2009
ACM
14 years 1 months ago
2009
ACM
This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to inte...
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
DAC
2006
ACM
13 years 9 months ago
2006
ACM
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...