45 search results - page 7 / 9 » A low-power clock frequency multiplier |
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
TMC
2008
13 years 8 months ago
2008
Mutual network synchronization is a distributed method in which geographically separated clocks align their times to one another without the need of reference or master clocks. Mut...
ET
2002
13 years 8 months ago
2002
LVDS is the acronym for Low-Voltage-DifferentialSignaling and is described in both the ANSI/TIA/EIA644 and IEEE 1596.3 standards. High performance yet Low Power and EMI have made ...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
Moore’s Law states that the number of transistors on a device doubles every two years; however, it is often (mis)quoted based on its impact on CPU performance. This important co...
FPL
1995
Springer
14 years 2 days ago
1995
Springer
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock ...