76 search results - page 10 / 16 » A methodology to improve timing yield in the presence of pro... |
ATS
2004
IEEE
13 years 11 months ago
2004
IEEE
An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that r...
ICNP
2006
IEEE
14 years 1 months ago
2006
IEEE
— Internet routers today can be overwhelmed by a large number of BGP updates triggered by events such as session resets, link failures, and policy changes. Such excessive updates...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
DAC
2007
ACM
13 years 11 months ago
2007
ACM
This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical...