76 search results - page 11 / 16 » A methodology to improve timing yield in the presence of pro... |
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...
ATS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confid...
ECCV
2004
Springer
14 years 25 days ago
2004
Springer
Abstract. Temporal random variation of luminance in images can manifest in film and video due to a wide variety of sources. Typical in archived films, it also affects scenes rec...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...