76 search results - page 12 / 16 » A methodology to improve timing yield in the presence of pro... |
DATE
2010
IEEE
14 years 16 days ago
2010
IEEE
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical planarization (CMP) to remove excess of deposited oxide and attain a planar...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
— In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly highe...
DATE
2010
IEEE
14 years 16 days ago
2010
IEEE
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...