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ICFEM
2004
Springer
14 years 4 months ago
Memory-Model-Sensitive Data Race Analysis
Abstract. We present a “memory-model-sensitive” approach to validating correctness properties for multithreaded programs. Our key insight is that by specifying both the inter-t...
Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom
MOMPES
2008
IEEE
14 years 5 months ago
Architectural Concurrency Equivalence with Chaotic Models
During its lifetime, embedded systems go through multiple changes to their runtime architecture. That is, threads, processes, and processor are added or removed to/from the softwa...
Dionisio de Niz
IEEEPACT
2009
IEEE
14 years 5 months ago
Analytical Modeling of Pipeline Parallelism
Parallel programming is a requirement in the multi-core era. One of the most promising techniques to make parallel programming available for the general users is the use of parall...
Angeles G. Navarro, Rafael Asenjo, Siham Tabik, Ca...
FCCM
2008
IEEE
205views VLSI» more  FCCM 2008»
14 years 5 months ago
Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation
The recent turmoil in global credit markets has demonstrated the need for advanced modelling of credit risk, which can take into account the effects of changing economic condition...
David B. Thomas, Wayne Luk
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
14 years 5 months ago
Copy or Discard execution model for speculative parallelization on multicores
The advent of multicores presents a promising opportunity for speeding up sequential programs via profile-based speculative parallelization of these programs. In this paper we pr...
Chen Tian, Min Feng, Vijay Nagarajan, Rajiv Gupta