28 search results - page 4 / 6 » A multi-level static memory cell |
GLVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Intrinsic variations and challenging leakage control in today’s bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRA...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is...
WADS
2009
Springer
14 years 2 months ago
2009
Springer
Abstract. Algorithms dealing with massive data sets are usually designed for I/O-efficiency, often captured by the I/O model by Aggarwal and Vitter. Another aspect of dealing with ...
MICRO
1997
IEEE
13 years 12 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...