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CODES
2004
IEEE
13 years 11 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
SDM
2009
SIAM
170views Data Mining» more  SDM 2009»
14 years 4 months ago
Optimal Distance Bounds on Time-Series Data.
Most data mining operations include an integral search component at their core. For example, the performance of similarity search or classification based on Nearest Neighbors is ...
Michail Vlachos, Philip S. Yu, Suleyman S. Kozat
ISLPED
2004
ACM
102views Hardware» more  ISLPED 2004»
14 years 1 months ago
Microarchitectural power modeling techniques for deep sub-micron microprocessors
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...
Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M...
ISPASS
2010
IEEE
14 years 2 months ago
Cache contention and application performance prediction for multi-core systems
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
Chi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley M...
WSC
2007
13 years 10 months ago
Ant-based approach for determining the change of measure in importance sampling
Importance Sampling is a potentially powerful variance reduction technique to speed up simulations where the objective depends on the occurrence of rare events. However, it is cru...
Poul E. Heegaard, Werner Sandmann