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ISPD
2012
ACM
283views Hardware» more  ISPD 2012»
12 years 3 months ago
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...
Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-H...
DAC
2007
ACM
14 years 8 months ago
Gate Sizing For Cell Library-Based Designs
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shif...
Shiyan Hu, Mahesh Ketkar, Jiang Hu
TASE
2008
IEEE
13 years 7 months ago
Group Elevator Scheduling With Advance Information for Normal and Emergency Modes
Group elevator scheduling has long been recognized as an important problem for building transportation efficiency, since unsatisfactory elevator service is one of the major complai...
Peter B. Luh, Bo Xiong, Shi-Chung Chang
CVPR
2009
IEEE
15 years 2 months ago
A Min-Max Framework of Cascaded Classifier with Multiple Instance Learning for Computer Aided Diagnosis
The computer aided diagnosis (CAD) problems of detecting potentially diseased structures from medical images are typically distinguished by the following challenging characterist...
Dijia Wu (Rensselaer Polytechnic Institute), Jinbo...
BMCBI
2005
162views more  BMCBI 2005»
13 years 7 months ago
Accelerated probabilistic inference of RNA structure evolution
Background: Pairwise stochastic context-free grammars (Pair SCFGs) are powerful tools for evolutionary analysis of RNA, including simultaneous RNA sequence alignment and secondary...
Ian Holmes