As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
—In this paper we compare and enhance the three prevailing approaches of IEEE 802.11e Performance analysis. Specifically, the first model utilizes a Markov Chain to describe th...
Ioannis Papapanagiotou, Georgios S. Paschos, Stavr...
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-...
Abstract— This paper proposes an approach to learn subjectindependent P300 models for EEG-based brain-computer interfaces. The P300 models are first learned using a pool of exis...
Plenty of work was contributed in the field of protocol design and performance evaluation of multi-hop networks. It is generally accepted that mobility has a huge impact on the p...
Frank H. P. Fitzek, Leonardo Badia, Michele Zorzi,...