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RTSS
2006
IEEE
14 years 1 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 21 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ASPLOS
2006
ACM
13 years 9 months ago
Tradeoffs in fine-grained heap memory protection
Different uses of memory protection schemes have different needs in terms of granularity. For example, heap security can benefit from chunk separation (by using protected "pa...
Jianli Shen, Guru Venkataramani, Milos Prvulovic
ATAL
2005
Springer
14 years 1 months ago
Improving reinforcement learning function approximators via neuroevolution
Reinforcement learning problems are commonly tackled with temporal difference methods, which use dynamic programming and statistical sampling to estimate the long-term value of ta...
Shimon Whiteson
IFIP3
1998
151views Education» more  IFIP3 1998»
13 years 9 months ago
Conceptual Workflow Modelling for Remote Courses
Development of a wide spread project intended to teaching Computer Science, integrating a considerable number of students all over a country with big geographical extension and sc...
José Palazzo M. de Oliveira, Mariano Nicola...