Sciweavers

3431 search results - page 24 / 687
» A new instructional operating system
Sort
View
ASPLOS
2006
ACM
14 years 1 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
CASES
2000
ACM
13 years 11 months ago
Flexible instruction processors
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
CASES
2006
ACM
14 years 1 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
IPPS
2006
IEEE
14 years 1 months ago
Web server protection by customized instruction set encoding
We present a novel technique to secure the execution of a processor against the execution of malicious code (trojans, viruses). The main idea is to permute parts of the opcode val...
Bernhard Fechner, Jörg Keller, Andreas Wohlfe...
SIGCSE
2004
ACM
141views Education» more  SIGCSE 2004»
14 years 1 months ago
Running on the bare metal with GeekOS
Undergraduate operating systems courses are generally taught e of two approaches: abstract or concrete. In the approach, students learn the concepts underlying operating systems t...
David Hovemeyer, Jeffrey K. Hollingsworth, Bobby B...