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IEEEPACT
2005
IEEE
14 years 2 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
CONNECTION
2006
172views more  CONNECTION 2006»
13 years 9 months ago
Temporal sequence detection with spiking neurons: towards recognizing robot language instructions
We present an approach for recognition and clustering of spatio temporal patterns based on networks of spiking neurons with active dendrites and dynamic synapses. We introduce a n...
Christo Panchev, Stefan Wermter
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 3 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
ASC
2004
13 years 9 months ago
Efficient fuzzy compiler for SIMD architectures
Abstract. This paper presents a real-time full-programmable fuzzy compiler based on piecewise linear interpolation techniques designed to be executed in SIMD (Single Instruction Mu...
Enrique Frías-Martínez, Julio Guti&e...
TOPLAS
1998
52views more  TOPLAS 1998»
13 years 8 months ago
Within ARM's Reach: Compilation of Left-Linear Rewrite Systems via Minimal Rewrite Systems
A new compilation technique for left-linear term-rewriting systems is presented, where rewrite rules are transformed into so-called minimal rewrite rules. These minimal rules have...
Wan Fokkink, Jasper Kamperman, Pum Walters