179 search results - page 18 / 36 » A new test pattern generation method for delay fault testing |
DSD
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
ET
2010
13 years 7 months ago
2010
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
ICCAD
1994
IEEE
14 years 26 days ago
1994
IEEE
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
DAC
1996
ACM
14 years 26 days ago
1996
ACM
The testability of basic DSP datapath structures using pseudorandom built-in self-test techniques is examined. The addition of variance mismatched signals is identified as a testi...
ECOOP
2006
Springer
14 years 12 days ago
2006
Springer
A test case consists of two parts: a test input to exercise the program under test and a test oracle to check the correctness of the test execution. A test oracle is often in the f...