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» A new test pattern generation method for delay fault testing
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VTS
1999
IEEE
71views Hardware» more  VTS 1999»
13 years 12 months ago
Test Generation for Ground Bounce in Internal Logic Circuitry
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is propose...
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
ICECCS
2002
IEEE
85views Hardware» more  ICECCS 2002»
14 years 16 days ago
Syntactic Fault Patterns in OO Programs
Although program faults are widely studied, there are many aspects of faults that we still do not understand, particularly about OO software. In addition to the simple fact that o...
Roger T. Alexander, Jeff Offutt, James M. Bieman
ATS
2009
IEEE
111views Hardware» more  ATS 2009»
14 years 2 months ago
Dynamic Compaction in SAT-Based ATPG
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
Alejandro Czutro, Ilia Polian, Piet Engelke, Sudha...
DSD
2005
IEEE
96views Hardware» more  DSD 2005»
13 years 9 months ago
Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
Peter Filter, Hana Kubatova
ATS
2009
IEEE
135views Hardware» more  ATS 2009»
14 years 2 months ago
On Scan Chain Diagnosis for Intermittent Faults
Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Sca...
Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, E...