179 search results - page 25 / 36 » A new test pattern generation method for delay fault testing |
DAC
1997
ACM
13 years 11 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents 3LSSD, a novel, easilyautomatable approach for scan insertion and ATPG of asynchronous circuits. 3LSSD inserts scan latches only into global circuit feedback p...
DELTA
2008
IEEE
14 years 2 months ago
2008
IEEE
Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, ...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal ...
CP
2009
Springer
14 years 8 months ago
2009
Springer
The goal of testing is to distinguish between a number of hypotheses about a systemfor example, dierent diagnoses of faults by applying input patterns and verifying or falsifying t...