179 search results - page 26 / 36 » A new test pattern generation method for delay fault testing |
ITC
2000
IEEE
13 years 11 months ago
2000
IEEE
1 The term "functional BIST" describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within ...
ET
2002
13 years 7 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
DDECS
2006
IEEE
14 years 1 months ago
2006
IEEE
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
DATE
2010
IEEE
14 years 19 days ago
2010
IEEE
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
ICCD
2003
IEEE
14 years 25 days ago
2003
IEEE
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...