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» A novel deadlock avoidance algorithm and its hardware implem...
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ICS
2000
Tsinghua U.
13 years 11 months ago
Improving parallel system performance by changing the arrangement of the network links
The Midimew network is an excellent contender for implementing the communication subsystem of a high performance computer. This network is an optimal 2D topology in the sense ther...
Valentin Puente, Cruz Izu, José A. Gregorio...
ISCA
2009
IEEE
186views Hardware» more  ISCA 2009»
14 years 2 months ago
Application-aware deadlock-free oblivious routing
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edwa...
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
14 years 1 months ago
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model
Abstract— Routing tree construction is a fundamental problem in modern VLSI design. In this paper we propose CDCTree, an Obstacle-Avoiding Rectilinear Steiner Minimum Tree (OARSM...
Yiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlo...
DATE
2007
IEEE
78views Hardware» more  DATE 2007»
14 years 1 months ago
Hardware scheduling support in SMP architectures
In this paper we propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified b...
André C. Nácul, Francesco Regazzoni,...
CODES
2005
IEEE
14 years 1 months ago
Novel architecture for loop acceleration: a case study
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
Seng Lin Shee, Sri Parameswaran, Newton Cheung