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» A novel high throughput reconfigurable FPGA architecture
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FPL
2008
Springer
125views Hardware» more  FPL 2008»
13 years 9 months ago
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks
FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconf...
Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dud...
DAC
2007
ACM
14 years 8 months ago
Enhancing FPGA Performance for Arithmetic Circuits
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To ad...
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Par...
FPL
2008
Springer
117views Hardware» more  FPL 2008»
13 years 9 months ago
On-the-fly attestation of reconfigurable hardware
This paper presents a novel method to perform on-the-fly attestation of hardware structures loaded to reconfigurable devices. Given that a loadable hardware structure to a reconfi...
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa
DAC
2006
ACM
14 years 8 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
ASPDAC
2011
ACM
215views Hardware» more  ASPDAC 2011»
12 years 11 months ago
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama...