252 search results - page 29 / 51 » A novel high throughput reconfigurable FPGA architecture |
CHES
2007
Springer
14 years 3 months ago
2007
Springer
Abstract. This paper presents a design-space exploration of the Galois/Counter Mode (GCM) algorithm with Advanced Encryption Standard (AES) as underlying block cipher for high thro...
DSD
2004
IEEE
14 years 16 days ago
2004
IEEE
Recently ultra-wideband (UWB) communications has emerged as an alternative to narrowband communications used in wireless sensor networks. One of UWB(s) most attractive feature for...
VLSID
2004
IEEE
14 years 9 months ago
2004
IEEE
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
CORR
2010
Springer
13 years 9 months ago
2010
Springer
Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the soft...