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» A novel improvement technique for high-level test synthesis
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ICSM
2005
IEEE
14 years 1 months ago
Test Suite Reduction with Selective Redundancy
Software testing is a critical part of software development. Test suite sizes may grow significantly with subsequent modifications to the software over time. Due to time and res...
Dennis Jeffrey, Neelam Gupta
ICIP
2009
IEEE
13 years 5 months ago
Improving the quality of depth image based rendering for 3D Video systems
In 3D Video (3DV) applications, a reduced number of views plus depth maps are transmitted or stored. When there is a need to render virtual views in between the actual views, the ...
Zefeng Ni, Dong Tian, Sitaram Bhagavathy, Joan Lla...
DSD
2007
IEEE
120views Hardware» more  DSD 2007»
14 years 2 months ago
Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction
The reduction of the cumbersome operations of multiplication, division, and powering to addition, subtraction and multiplication is what makes the Logarithmic Number System (LNS) ...
Panagiotis D. Vouzis, Sylvain Collange, Mark G. Ar...
VTS
2003
IEEE
95views Hardware» more  VTS 2003»
14 years 27 days ago
Built-In Reseeding for Serial Bist
Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost...
Ahmad A. Al-Yamani, Edward J. McCluskey
TVLSI
2010
13 years 2 months ago
Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods
Abstract--Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requiremen...
Kanad Basu, Prabhat Mishra