287 search results - page 38 / 58 » A novel improvement technique for high-level test synthesis |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
This paper presents a fast and scalable method of computing signal toggle rate in FPGA-based circuits. Our technique is a vectorless estimation technique, which can be used in a C...
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
We tackle the problem of fault-free assumptions in current PLB and interconnect built-in-self-test (BIST) techniques for FPGAs. These assumptions were made in order to develop stro...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
MASCOTS
2010
13 years 9 months ago
2010
To reduce cloud system resource cost, application consolidation is a must. In this paper, we present a novel patterndriven application consolidation (PAC) system to achieve efficie...