287 search results - page 9 / 58 » A novel improvement technique for high-level test synthesis |
FPL
2003
Springer
14 years 25 days ago
2003
Springer
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
GECCO
2006
Springer
13 years 11 months ago
2006
Springer
Achieving a high quality and cost-effective tests is a major concern for software buyers and sellers. Using tools and integrating techniques to carry out low cost testing are chal...
GLVLSI
2000
IEEE
14 years 21 hour ago
2000
IEEE
We present a novel global routing and cross-point assignment methodology for sea-of-gates (SOG) designs. Using the proposed congestion driven spanning trees (CDST), and continuous...
ENTCS
2002
13 years 7 months ago
2002
We present a novel technique called comparison checking that helps optimizer writers debug optimizers by testing, for given inputs, that the semantics of a program are not changed...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequ...