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» A novel technique for sea of gates global routing
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DAC
2009
ACM
14 years 8 months ago
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies ...
Jürgen Teich, Martin Lukasiewycz, Michael Gla...
ISVLSI
2007
IEEE
150views VLSI» more  ISVLSI 2007»
14 years 1 months ago
Minimum-Congestion Placement for Y-interconnects: Some studies and observations
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...
Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Pa...
TCAD
2008
167views more  TCAD 2008»
13 years 7 months ago
System-Level Dynamic Thermal Management for High-Performance Microprocessors
Abstract--Thermal issues are fast becoming major design constraints in high-performance systems. Temperature variations adversely affect system reliability and prompt worst-case de...
Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K....
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
13 years 11 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
ISPD
2007
ACM
116views Hardware» more  ISPD 2007»
13 years 9 months ago
A morphing approach to address placement stability
Traditionally, research in global placement has focused on relatively few simple metrics, such as pure wirelength or routability estimates. However, in the real world today, desig...
Philip Chong, Christian Szegedy