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CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ANCS
2005
ACM
14 years 1 months ago
SSA: a power and memory efficient scheme to multi-match packet classification
New network applications like intrusion detection systems and packet-level accounting require multi-match packet classification, where all matching filters need to be reported. Te...
Fang Yu, T. V. Lakshman, Martin Austin Motoyama, R...
PADS
2005
ACM
14 years 1 months ago
The WarpIV Simulation Kernel
ct This paper provides an overview of the WarpIV Simulation Kernel that was designed to be an initial implementation of the Standard Simulation Architecture (SSA). WarpIV is the ne...
Jeffrey S. Steinman
ISNN
2005
Springer
14 years 1 months ago
One-Bit-Matching ICA Theorem, Convex-Concave Programming, and Combinatorial Optimization
Recently, a mathematical proof is obtained in (Liu, Chiu, Xu, 2004) on the so called one-bit-matching conjecture that all the sources can be separated as long as there is an one-to...
Lei Xu
ISPA
2005
Springer
14 years 1 months ago
Ethernet as a Lossless Deadlock Free System Area Network
The way conventional Ethernet is used today differs in two aspects from how dedicated system area networks are used. Firstly, dedicated system area networks are lossless and only d...
Sven-Arne Reinemo, Tor Skeie
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