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» A performance analysis of local synchronization
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ISPD
2000
ACM
124views Hardware» more  ISPD 2000»
15 years 8 months ago
A performance optimization method by gate sizing using statistical static timing analysis
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
Masanori Hashimoto, Hidetoshi Onodera
ICS
2009
Tsinghua U.
15 years 10 months ago
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Jiayuan Meng, Kevin Skadron
DATE
2008
IEEE
115views Hardware» more  DATE 2008»
15 years 10 months ago
Synthesizing Synchronous Elastic Flow Networks
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
Greg Hoover, Forrest Brewer
ICRA
2000
IEEE
96views Robotics» more  ICRA 2000»
15 years 8 months ago
Design of Synchronized Supply Chains: A Six Sigma Tolerancing Approach
A supply chain network can be viewed as a network of facilities in which a customer order will flow through internal business processes such as procurement, production, and transp...
Y. Narahari, Nukala Viswanadham, R. Bhattacharya
GLOBECOM
2007
IEEE
15 years 10 months ago
Impact of Noisy Carrier Phase Synchronization on Linear Amplify-and-Forward Relaying
—We consider a distributed wireless network where amplify-and-forward relays assist the communication between multiple source/destination pairs. To provide a global phase referen...
Stefan Berger, Armin Wittneben