124 search results - page 7 / 25 » A power-configurable bus for embedded systems |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogene...
DAC
2008
ACM
13 years 9 months ago
2008
ACM
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation i...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be d...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
As memory speeds and bus capacitances continue to rise, external memory bus power will make up an increasing portion of the total system power budget for system-on-a-chip embedded...
DFT
2000
IEEE
13 years 11 months ago
2000
IEEE
We present a configuration technique for a Large Area Integrated Circuit (LAIC) which is manufactured by wafer stepping. A LAIC consists of four identical subsystems, i.e., a subs...