420 search results - page 21 / 84 » A pseudo-hierarchical methodology for high performance micro... |
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
BMCBI
2010
13 years 8 months ago
2010
Background: RNA structure prediction problem is a computationally complex task, especially with pseudo-knots. The problem is well-studied in existing literature and predominantly ...
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tigh...
DAC
1999
ACM
14 years 9 months ago
1999
ACM
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
CODES
1996
IEEE
14 years 24 days ago
1996
IEEE
Performance modeling and evaluation of embedded hardware/software systems is important to help the CoDesign process. The hardware/software partitioning needs to be evaluated befor...