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FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
14 years 1 months ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi
DAC
2008
ACM
14 years 9 months ago
The synthesis of robust polynomial arithmetic with stochastic logic
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
Weikang Qian, Marc D. Riedel
ATAL
2008
Springer
13 years 10 months ago
Using multi-agent potential fields in real-time strategy games
Bots for Real Time Strategy (RTS) games provide a rich challenge to implement. A bot controls a number of units that may have to navigate in a partially unknown environment, while...
Johan Hagelbäck, Stefan J. Johansson
ICCAD
2006
IEEE
152views Hardware» more  ICCAD 2006»
14 years 5 months ago
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...
Zhuo Feng, Peng Li
CODES
2009
IEEE
14 years 3 months ago
A high-level virtual platform for early MPSoC software development
Multiprocessor System-on-Chips (MPSoCs) are nowadays widely used, but the problem of their software development persists to be one of the biggest challenges for developers. Virtua...
Jianjiang Ceng, Weihua Sheng, Jerónimo Cast...