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» A reduction approach to the repeated assignment problem
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AUTOMATICA
2011
13 years 3 months ago
Sequential linear quadratic control of bilinear parabolic PDEs based on POD model reduction
We present a framework to solve a finite-time optimal control problem for parabolic partial differential equations (PDEs) with diffusivity-interior actuators, which is motivate...
Chao Xu, Yongsheng Ou, Eugenio Schuster
ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 5 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
CACM
2010
104views more  CACM 2010»
13 years 8 months ago
Faster dimension reduction
Data represented geometrically in high-dimensional vector spaces can be found in many applications. Images and videos, are often represented by assigning a dimension for every pix...
Nir Ailon, Bernard Chazelle
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 5 months ago
Soft error reduction in combinational logic using gate resizing and flipflop selection
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
DAC
2009
ACM
14 years 9 months ago
ILP-based pin-count aware design methodology for microfluidic biochips
Digital microfluidic biochips have emerged as a popular alternative for laboratory experiments. To make the biochip feasible for practical applications, pin-count reduction is a k...
Cliff Chiung-Yu Lin, Yao-Wen Chang