1017 search results - page 159 / 204 » A routing algorithm for flip-chip design |
SLIP
2009
ACM
14 years 2 months ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
GLVLSI
2003
IEEE
14 years 28 days ago
2003
IEEE
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
IPPS
2003
IEEE
14 years 28 days ago
2003
IEEE
One of the most important issues to deal with in peerto-peer networks is how to disseminate information. In this paper, we use a completely new approach to solving the information...
DATE
2002
IEEE
14 years 18 days ago
2002
IEEE
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...